Level shift circuit
US7663423B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 15, 2008 |
| Grant date | Feb 16, 2010 |
| Priority date | — |
| Expiry date | Dec 15, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356113
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A signal level shifting circuit, including an input stage circuit and an output signal latching circuit. The input stage circuit receives an input signal, wherein a voltage level of the input signal falls within a first predetermined voltage range. The output signal latching circuit is cascoded with the input stage circuit, and includes: a latching circuit for generating an output signal according to the input signal, wherein a voltage level of the output signal falls within a second predetermined voltage range, and the second predetermined voltage range is different from the first predetermined voltage range; and an activating circuit, coupled to the latching circuit, for selectively enabling or disabling the latching circuit, wherein when a level transition appears to the input signal, the activating circuit disables the latching circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.