Semiconductor memory with a delay circuit
US7663945B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2007 |
| Grant date | Feb 16, 2010 |
| Priority date | — |
| Expiry date | Oct 12, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell core unit. A sense amplifier amplifies a higher voltage level of a bit line to the power supply voltage. Then, a circuit for generating a signal for defining the transition timing and/or the pulse width of a control signal from the peripheral circuit to the cell core unit performs signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.