Memory with clock-controlled memory access and method of operating the same

US7663965B2 · kind B2 · utility

Assignee

• Qimonda AG · DE

Inventors

• Falk Roewer · Magdeburg, DE
• Florian Schnabel · Ehrenkirchen, DE
• Christian Sichert · Attenkirchen, DE

Key dates

• Filing date: Jun 11, 2007
• Grant date: Feb 16, 2010
• Expiry date: Apr 11, 2028

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C7/22
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An integrated circuit memory with clock-controlled memory access includes at least one data connection to input/output data, a memory cell array including memory cells to store data, a clock generator circuit to generate a clock signal, a memory circuit to store data, a control circuit to control storage of data in the memory circuit and to control output of data from the memory circuit. The memory circuit is connected to the memory cell array and to the at least one data connection. During read access to the memory cells, first and second data supplied to the memory circuit from the memory cell array are buffer-stored in the memory circuit upon first and second edges of the clock signal. The first and second data are output from the memory circuit and supplied to the at least one data connection upon third and fourth edges of the clock signal.