Receiver system having analog pre-filter and digital equalizer
US7664172B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2006 |
| Grant date | Feb 16, 2010 |
| Priority date | — |
| Expiry date | Aug 15, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03254
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A receiver system contains an analog pre-filter (207 or 619), an analog-to-digital converter (210), a digital equalizer (212), and a decoder (605) arranged sequentially for processing an input analog signal (yk). The pre-filter produces a filtered analog signal (Zs) with reduced intersymbol interference. The converter provides analog-to-digital signal conversion. Digital equalization circuitry in the equalizer operates according to a transfer frmnctionto produce an equalized digital signal (a'k) as a stream of equalized digital values. Coefficients c−1 and c0 are fixed. Each other coefficient ci is adaptively chosen. The decoder converts the equalized digital values, or intermediate values generated therefrom, into a stream of symbols. A receiver system may include two or more receivers each configured in the foregoing way with the digital equalization circuitry in each receiver operating according to a transfer functionwhere at least coefficients c−1, c0, and c1 are non-zero.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.