Adaptive timing using clock recovery
US7664204B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2005 |
| Grant date | Feb 16, 2010 |
| Priority date | — |
| Expiry date | Jun 28, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2027/0091
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Circuits and methods are provided for adjusting a frequency of a local clock signal in approximating a frequency of a host clock signal. A phase locked loop generates a local clock signal having a first phase and a first frequency. An offset adjustment circuit receives timing information relating the local clock signal to an incoming data signal and calculates a phase offset and a frequency offset indicative of adjustments to be made to the local clock signal. A first phase interpolator generates a receive clock signal from the local clock signal, the receive clock signal having a second phase and a second frequency responsive to the phase and frequency offsets. A second phase interpolator generates a transmit clock signal from the local clock signal having a third frequency responsive to the frequency offset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.