High performance raid-6 system architecture with pattern matching
US7664915B2 · kind B2 · utility
3Cited by
4References
24Claims
0Family size
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Key dates
| Filing date | Dec 19, 2006 |
| Grant date | Feb 16, 2010 |
| Priority date | — |
| Expiry date | Feb 19, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2211/1057
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An acceleration unit offloads computationally intensive tasks from a processor. The acceleration unit includes two data processing paths each having an Arithmetic Logical Unit and sharing a single multiplier unit. Each data processing path may perform configurable operations in parallel on a same data. Special multiplexer paths and instructions are provided to allow P and Q type syndromes to be computed on a stripe in a single-pass of the data through the acceleration unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.