Flash memory device with fast reading rate
US7664987B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2004 |
| Grant date | Feb 16, 2010 |
| Priority date | — |
| Expiry date | Jan 16, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1068
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of sending data from a memory to a host, and a data storage device that uses the method. The controller of the data storage device sends the data directly from the memory to a buffer in an interface to the host while simultaneously checking the data for errors. If sufficiently few errors are found, the data are sent from the buffer to the host. Otherwise, the data are corrected, the data in the buffer are replaced with the corrected data, and the corrected data are written to the memory. If the data are stored by segments, the simultaneous sending and checking is effected segmentwise. When a bad segment is found, an error flag is set. When all the data have been sent and checked, or when the buffer is full, if the error flag has not been set, the data in the buffer are sent to the host.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.