Method for performing post-synthesis circuit optimization
US7665047B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Oct 9, 2006 |
| Grant date | Feb 16, 2010 |
| Priority date | — |
| Expiry date | Oct 9, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Two methods for post-synthesis circuit optimization are disclosed. In both methods, the underlying variability in process parameters is captured through a robust linear program. The robust linear program is then reformulated as a second order conic program that possesses special structural properties to allow for a computationally efficient solution by using interior point optimization methods. The first method treats gate delays as uncertain quantities and obtains the optimal sizes for gates in a circuit under a probabilistically specified circuit timing target. The second method optimizes total circuit power by using a combination of dual threshold voltage assignment and gate sizing. Both circuit power and timing are treated probabilistically.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.