Circuit for detecting and measuring noise in semiconductor integrated circuit
US7667477B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 20, 2004 |
| Grant date | Feb 23, 2010 |
| Priority date | — |
| Expiry date | Jun 15, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Noise measuring circuitry of the present invention can be used to observe power supply noise waveforms, ground level noise waveforms, and a spatial distribution of noise at different positions in an integrated circuit having plural circuit blocks that perform digital signal processing, by being integrated into the integrated circuit (i.e., embedded), distributed at different positions. The distributed noise measuring circuitry can be manufactured using a CMOS process to manufacture the integrated circuit. The power supply noise measuring circuit and the ground level noise measuring circuit comprise a source follower, a select read out switch, and source-grounded amplifier. These noise measuring circuits can be configured by several (about 6) MOS transistors, so the layout for the measuring circuit can be small and can be achieved by using a logic gate circuit of the same size as that of a standard cell type logic gate circuit. As for the output of the noise measuring circuits, the output current of said source-grounded amplifier is connected to the current bus line, the outputted current is amplified and the amplified current is read by driving the external resistance load circuit.…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.