Hardware implementation of network testing and performance monitoring in a network device
US7668107B2 · kind B2 · utility
5Cited by
2References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2006 |
| Grant date | Feb 23, 2010 |
| Priority date | — |
| Expiry date | Sep 21, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L43/50
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An embodiment of the present invention offloads the generation and monitoring of test packets from a Central processing Unit (CPU) to a dedicated network integrated circuit, such as a router, bridge or switch chip associated with the CPU. The CPU may download test routines and test data to the network IC, which then generates the test packets, identifies and handles received test packets, collects test statistics, and performs other test functions all without loading the CPU. The CPU may be notified when certain events occur, such as when throughput or jitter thresholds for the network are exceeded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.