Apparatus and method for clock data recovery with low lock frequency
US7668277B2 · kind B2 · utility
1Cited by
6References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 18, 2006 |
| Grant date | Feb 23, 2010 |
| Priority date | — |
| Expiry date | Apr 24, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/047
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
For clock and data recovery (CDR), a clock processor generates sampling clock signals from original phase-shifted clock signals each having a frequency that ⅛ of a frequency of an input data signal. The sampling clock signals are used to sample the input data signal for generating error signals and reference signals that determine a voltage control signal that indicates a clock frequency of the original clock signals generated by a voltage controlled oscillator (VCO).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.