Phase-locked loop
US7668278B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2004 |
| Grant date | Feb 23, 2010 |
| Priority date | — |
| Expiry date | Jul 16, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0898
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An oscillator (30) supplies a high frequency signal (S) to a frequency divider (31). A phase comparator (32) produces a signal measuring phase difference between the divided frequency signal (QA) and a reference signal. A low-pass filter (34) controls the oscillator on the basis of the measurement signal. A measurement window, of duration defined by counting cycles of the high frequency signal, is generated in response to each active edge of the divided frequency signal. The measurement signal is activated during the measurement window so that it comprises, when an active edge of the reference signal falls within the window, a first pulse between the start of the window and this edge and a second pulse, opposite to the first, between this edge and the end of the window.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.