Method and circuit for detecting and compensating for a degradation of a semiconductor device
US7668682B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2007 |
| Grant date | Feb 23, 2010 |
| Priority date | — |
| Expiry date | Dec 7, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2837
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A design structure and method comprising a degradation detection circuit configured to respond to degradation. The degradation detection circuit is located within a semiconductor device and comprises a process sensitive circuit, a measurement circuit, a calculation circuit, and a control circuit. The method comprises subjecting the semiconductor device to a first operating condition. A first value at a first time for a parameter of the process sensitive circuit is measured by the measurement circuit. The semiconductor device is operated to perform an intended function. A second value at a second time for the parameter of the circuit is measured by the measurement circuit. The second time is different from the first time. A first differential value between the first value and the second value is determined by the calculation circuit. The control circuit is configured to receive an enable signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.