Duty cycle calibration for receiver clock
US7668698B2 · kind B2 · utility
6Cited by
2References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 6, 2007 |
| Grant date | Feb 23, 2010 |
| Priority date | — |
| Expiry date | Dec 16, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/135
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention are generally directed to systems, methods, and apparatuses for the direct duty cycle calibration of a receiver clock. In some embodiments, an integrated circuit includes a receive (RX) data path, a RX clock path, and a control path. In some embodiments, the control path uses RX latches, a majority detector, and digital duty cycle control logic to calibrate the duty cycle of the clock signal. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.