Data bus inversion detection mechanism
US7668988B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 19, 2007 |
| Grant date | Feb 23, 2010 |
| Priority date | — |
| Expiry date | May 21, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/607
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus inversion apparatus includes exclusive-OR gates and an inversion detector. The exclusive-OR gates are coupled to an instant data bus and a last data bus. The data buses have a corresponding plurality of bits, where the exclusive-OR gates perform a bitwise comparison of the data buses, and provide an exclusive-OR bus. The states of the exclusive-OR bus indicate whether corresponding bits of the data buses are different. The inversion detector counts the number of the corresponding bits that are different, and indicates that the instant data bus should be inverted. The inversion detector has a plurality of left shift circuits, each configured to perform a logical left shift of input bits as directed by the states of shift bits, where outputs of the each of the plurality of left shift circuits indicate a number of a subgroup of the corresponding bits that are different.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.