Clock circuitry architecture to improve electro-magnetic compatibility and optimize peak of currents in micro-controller
US7669072B2 · kind B2 · utility
2Cited by
4References
16Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 30, 2007 |
| Grant date | Feb 23, 2010 |
| Priority date | — |
| Expiry date | Aug 8, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system comprises a central processing unit and a set of peripheral units accessible by the CPU and being able to be driven by the same clock source. At least one programmable delay line is located in the clock branch of one of the peripheral units and has a delay selection input that is accessible by software running on the system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.