Methods and apparatus for error injection
US7669095B2 · kind B2 · utility
6Cited by
9References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2006 |
| Grant date | Feb 23, 2010 |
| Priority date | — |
| Expiry date | Mar 2, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L43/50
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In a first aspect, a first method of injecting one or more errors in data flowing into or out of a chip is provided. The first method includes the steps of (1) generating an error injection pattern indicating one or more bits of data on which a pseudo-random error is to be inserted; and (2) generating an error injection trigger indicating when the pseudo-random error is to be inserted. Numerous other aspects are provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.