Forward error correction method and communication method, and forward error correction code addition apparatus and communication apparatus
US7669104B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2005 |
| Grant date | Feb 23, 2010 |
| Priority date | — |
| Expiry date | Jan 3, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/1867
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In a forward error correction method and a forward error correction addition apparatus, error correction is performed on the basis of data, to which forward error correction code is added, transmitted through a network to output decoded data. The data transmitted through the network includes information bits represented by an information bit matrix with n rows and m columns (n, m are natural numbers), and redundancy bits represented by an odd number of redundancy information bit rows and an odd number of redundancy information bit columns based on the information bit matrix, which are provided in the row direction and in the column direction of the information bit matrix respectively. The redundancy bits are the forward error correction code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.