Methods for reducing power supply simultaneous switching noise
US7669151B1 · kind B1 · utility
6Cited by
9References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 7, 2007 |
| Grant date | Feb 23, 2010 |
| Priority date | — |
| Expiry date | Mar 31, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Computer-aided design tools analyze a custom logic design for a programmable logic device integrated circuit. The tools identify distinct clock domains in the design. The tools also identify which of the clock domains are synchronous. The tools examine the synchronous clock domains to determine which of the clock domains have required fixed phase relationships. Clocks for clock domains that do not have required fixed relationships can be adjusted in phase to minimize power supply simultaneous switching noise. Noise may be minimized by making clock phase adjustments using a programmable phase-locked loop circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.