Methods for verifying correct counter-bore depth and precision on printed circuit boards
US7669321B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2006 |
| Grant date | Mar 2, 2010 |
| Priority date | — |
| Expiry date | Feb 3, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T408/175
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A test site is incorporated on a circuit board having a set of test connections passing through a test via on respective test connection layer, the test connection layers including (1) a first layer adjacent to a target layer, and (2) a second layer spaced apart from the target layer with the first layer therebetween. The test via is back-drilled from the direction of the second layer to remove undesired via metallization, breaking the test connections of all the layers through which it passes, and the continuity of the test connections is measured to determine a pattern of broken and non-broken test connections resulting from the back-drilling. The pattern of broken and non-broken test connections is examined to ascertain the actual depth of the back-drilling in relation to the target layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.