Plating method, semiconductor device fabrication method and circuit board fabrication method
US7670940B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2005 |
| Grant date | Mar 2, 2010 |
| Priority date | — |
| Expiry date | May 16, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/0228
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The plating method comprises the step of forming a resin layer 10 over a substrate 16; the step of cutting the surface part of the resin layer 10 with a cutting tool 12; the step of forming a seed layer 36 on the resin layer 10 by electroless plating; and the step of forming a plating film 44 on the seed layer 36 by electroplating. Suitable roughness can be give to the surface of the resin layer 10, whereby the adhesion between the seed layer 36 and the resin layer 10 can be sufficiently ensured. Excessively deep pores are not formed in the surface of the resin layer 10, as are by desmearing treatment, whereby a micronized pattern of a photoresist film 40 can be formed on the resin layer 10. Thus, interconnections 44, etc. can be formed over the resin layer 10 at a narrow pitch with high reliability ensured.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.