Semiconductor storage device
US7671399B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2006 |
| Grant date | Mar 2, 2010 |
| Priority date | — |
| Expiry date | Dec 24, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6891
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor storage device in which product cost is reduced includes a memory cell section (cells belonging to word lines) and a bypass section (cells belonging to bypass word lines). The memory cell section has a select gate, floating gates, a first diffusion region, a second diffusion region and a first control gate. The bypass section has the first select gate, the first diffusion region, the second diffusion region and a second control gate. The second control gate controls a channel in an area between the select gate and the first diffusion region or between the select gate and the second diffusion region. The channel of the bypass section becomes a current supply path when a cell of the memory cell section is read out.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.