Patent · US Active

Buried via technology for three dimensional integrated circuits

US7671460B2 · kind B2 · utility

244Cited by

27References

19Claims

0Family size

Assignee

Teledyne Licensing, LLC · US

Inventors

Stefan C. Lauxtermann · Porta Westfalica, DE
Jeffrey F. DeNatale · Thousand Oaks, US

Key dates

Filing date	Jan 18, 2007
Grant date	Mar 2, 2010
Priority date	—
Expiry date	May 5, 2028

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/00014
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A three dimensional integrated circuit and method for making the same. The three dimensional integrated circuit has a first and a second active circuit layers with a first metal layer and a second metal layer, respectively. The metal layers are connected by metal inside a buried via. The fabrication method includes etching a via in the first active circuit layer to expose the first metal layer without penetrating the first metal layer, depositing metal inside the via, the metal inside the via being in contact with the first metal layer, and bonding the second active circuit layer to the first active circuit layer using a metal bond that connects the metal inside the via to the second metal layer of the second active circuit layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.