Redundant clock switch circuit
US7671634B2 · kind B2 · utility
4Cited by
6References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 30, 2007 |
| Grant date | Mar 2, 2010 |
| Priority date | — |
| Expiry date | Jul 30, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A redundant clock switch circuit that includes two delay circuits and control logic is presented. The first delay circuit is configured to delay a first clock signal to produce a first delayed clock signal, while the second delay circuit is configured to delay a second clock signal to produce a second delayed clock signal. The control logic is configured to control the delay circuits to maintain phase alignment between the first and second delayed clock signals. The control logic is also configured to select one of the first and second delayed clock signals as an output clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.