Frequency divider
US7671641B1 · kind B1 · utility
5Cited by
4References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2005 |
| Grant date | Mar 2, 2010 |
| Priority date | — |
| Expiry date | Mar 4, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356121
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency divider includes a first latch and a second latch. The first latch is configured to receive a clock signal. The first latch is cross-coupled to the second latch. The second latch includes a circuit configured as a low-pass filter. The second latch further includes a differential pair of transistors. Each of the transistors include a drain, a source and a gate. The gates of the at least two transistors configured to receive a signal generated by the first latch. Additionally, the gates of the at least two other transistors are coupled to a control signal for determining a low-pass characteristic of the second latch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.