Digital signal processing scheme for high performance HFC digital return path system with bandwidth conservation
US7671778B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2003 |
| Grant date | Mar 2, 2010 |
| Priority date | — |
| Expiry date | Dec 30, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/6168
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In a cable return path system, a method for performing digital companding adds a predetermined offset to the digital value to be companded, and employs a modified μ-law or a-law companding technique to obtain a reduced bit length digital value. One embodiment of this modified approach adds a predetermined offset (e.g., 129 for a 12-bit implementation) to the digital value before companding and then employs a two-bit chord and a 5-bit step for the 12-bit implementation. The end result is that the performance metrics are not significantly compromised by this bit reduction when compared to current transmission methods without this technique.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.