Solid-state imaging apparatus
US7671912B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2003 |
| Grant date | Mar 2, 2010 |
| Priority date | — |
| Expiry date | Dec 9, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/134
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A solid-state imaging device capable of simplifying a pixel structure to reduce a pixel size and capable of suppressing a variation in characteristics between pixels when a plurality of output systems are provided. A unit cell includes two pixels having upper and lower photoelectric converters, transfer transistors connected to the upper and lower photoelectric converters, a reset transistor, and an amplifying transistor. A full-face signal line is connected to the respective drains of the reset transistor and the amplifying transistor. Controlling the full-face signal line along with transfer signal lines and a reset signal line to read out signals simplifies wiring in the pixel and permits reduction of the pixel size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.