Patent · US Active

Electrostatic discharge protection structures with reduced latch-up risks

US7672100B2 · kind B2 · utility

42Cited by

2References

17Claims

0Family size

Assignee

SOFICS BVBA · BE

Inventor

Benjamin Van Camp · Brugge, BE

Key dates

Filing date	May 22, 2007
Grant date	Mar 2, 2010
Priority date	—
Expiry date	Mar 11, 2028

Classification

Technology area (CPC H)Electricity
CPC primaryH02H9/046
WIPO fieldElectrical machinery, apparatus, energy
WIPO sectorElectrical engineering

Abstract

The present invention provides an ESD protection circuitry in a semiconductor integrated circuit (IC) having protected circuitry to prevent false triggering of the ESD clamp. The circuitry includes an SCR as an ESD clamp having an anode adapted for coupling to a first voltage source, and a cathode adapted for coupling to a second voltage source. The circuitry also includes at least one noise current buffer (NCB) coupled between at least one of a first trigger tap of the SCR and the first voltage source such that the first trigger tap of the SCR is coupled to a power supply.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.