Memory device and method thereof
US7672177B2 · kind B2 · utility
1Cited by
2References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 31, 2007 |
| Grant date | Mar 2, 2010 |
| Priority date | — |
| Expiry date | Oct 3, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device and a method thereof. The memory described includes a control module and a single-port memory array. The control circuit generates control signals according to a clock signal, a read command signal and a write command signal. The single-port memory array is accessed according to the control signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.