Methods and apparatus for deskewing VCAT/LCAS members
US7672315B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2005 |
| Grant date | Mar 2, 2010 |
| Priority date | — |
| Expiry date | Dec 24, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J2203/0094
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Write logic and read logic are coupled to SDRAM and a frame status table. VCG members are written into SDRAM by the write logic and an entry (based on the MFI and SQ) in the frame status table is maintained by the write logic for each member. The read logic scans the frame status table to identify the earliest frame number for which data is available in SDRAM. Based on the frame status and the address pointer offset, the read logic maintains a state table entry for each VCG member and a state for each VCG. According to the preferred embodiment, the read logic is provided in two parts separated by a temporary buffer. The first part of the read logic performs the functions described above and writes chunk data into the temporary buffer. The second part of the read logic reads byte data from the temporary buffer according to a selectable leak rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.