Clock and data recovery circuit and SERDES circuit
US7672406B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 4, 2007 |
| Grant date | Mar 2, 2010 |
| Priority date | — |
| Expiry date | Oct 23, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0025
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is a clock-and-data recover circuit in which a data sampling circuit, a phase comparator, a phase controller and a phase interpolator make up a loop. The data sampling circuit samples serial input data, and the phase comparator receives an output from the data sampling circuit to detect the phase relationship between clock and the data. The phase controller outputs a phase control signal based on the result of phase comparison of the phase comparator to output a phase control signal. The phase interpolator receives a multi-phase clock composed of plural clock signals with different phases and supplies a clock signal having the phase interpolated based on the phase control signal, to the data sampling circuit. The clock and data recovery circuit further includes a second phase interpolator and a second data sampling circuit. The phase controller generates and outputs a second phase control signal to the second phase interpolator. The second phase interpolator receives the multi-phase clock and outputs a second clock signal having the phase interpolated based on the second phase control signal and supplies the second clock signal to the second data sampling circuit. The sec…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.