Clock and data recovery
US7672417B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2006 |
| Grant date | Mar 2, 2010 |
| Priority date | — |
| Expiry date | Oct 8, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0041
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data and clock recovery circuit having a retimer mode and a resync mode. In one embodiment, a receiver circuit includes; a retimer; a clock recovery circuit to provide a clock signal to the retimer; and an adjustable delay to provide a delayed version of an input signal to the retimer. When in a resync mode, the adjustable delay causes a pre-selected delay in the input signal and the clock recovery circuit dynamically selects a clock phase to generate the clock signal. When in a second mode, the adjustable delay dynamically adjusts the delayed version of the input signal and the clock recovery circuit outputs the clock signal having a pre-selected clock phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.