Secure scan
US7672452B2 · kind B2 · utility
1Cited by
27References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 1, 2003 |
| Grant date | Mar 2, 2010 |
| Priority date | — |
| Expiry date | May 29, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/26
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
According to the invention, a circuit that is capable of automated scan testing is disclosed. Included in the circuit are a cryptographic engine, a digital circuit, an input pin, and an output pin. The cryptographic engine capable of performing at least one of encryption and decryption of one or more digital signals. The digital circuit includes combinatorial logic and a number of memory cells. The memory cells have scan inputs connected serially in a scan chain. The input pin and output pin are coupled to the scan chain. At least one of the input pin and the output pin carries at least some cipher text data of the scan chain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.