Low power chip architecture
US7672694B2 · kind B2 · utility
0Cited by
8References
8Claims
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Assignee
Inventors
Key dates
| Filing date | Jun 30, 2004 |
| Grant date | Mar 2, 2010 |
| Priority date | — |
| Expiry date | Jun 14, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An architecture for selectively powering a receive module (108) is disclosed. The architecture comprises the receive module (108) which is functionally adapted, while power is applied to the receive module (108) by a power module (601), and after a power-up time interval has elapsed, to process a traffic packet. The architecture further comprises the power module (601) that is adapted to apply power to the receive module 108 dependent upon arrival of a wake-up packet.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.