Large number multiplication method and device
US7672989B2 · kind B2 · utility
2Cited by
8References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 8, 2006 |
| Grant date | Mar 2, 2010 |
| Priority date | — |
| Expiry date | Dec 31, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/525
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A signed multiplication method and a corresponding device for multiplying a first multiplicand with a second multiplicand. The device stores the first multiplicand in a first register as a first vector of at least one respective digit and storing the second multiplicand in a second register as a second vector of at least one respective digit, each digit having a pre-determined number of bits. The method further converts the digits of the first vector and the second vector to corresponding digits of one bit less each than the pre-determined number of bits. A processor effects signed multiplication of the multiplicands.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.