FIFO memory architecture and method for the management of the same
US7673095B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 17, 2004 |
| Grant date | Mar 2, 2010 |
| Priority date | — |
| Expiry date | Apr 19, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A FIFO memory with a frequency f and a size of M n-bit words, to successively store n-bit words received serially at an input and give said words serially at an output in the order in which they are stored, comprises a basic memory with a frequency f/2, capable of simultaneously storing two n-bit words successively received at the input of the FIFO memory. The memory also comprises a storage circuit to store either one n-bit word received at the input of the FIFO memory or simultaneously two n-bit words produced by the basic memory and to produce, at the output OUT of the FIFO memory, one of the words that said storage circuit stores.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.