Inter-cluster communication network and heirarchical register files for clustered VLIW processors
US7673120B2 · kind B2 · utility
3Cited by
6References
6Claims
0Family size
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Key dates
| Filing date | Jun 27, 2007 |
| Grant date | Mar 2, 2010 |
| Priority date | — |
| Expiry date | Jun 10, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3891
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A VLIW processor has a hierarchy of functional unit clusters that communicate through explicit control in the instruction stream and store data in register files at each level of the hierarchy. Explicit instructions transfer values between sub-clusters through a cluster level switch network. Transfer instructions issue in dedicated instruction issue slots in parallel with instructions that perform computation in functional units. The switch network can perform permutations on the data being moved. The switch network enables for operands to be broadcast between the sub-clusters, global register file and memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.