Managing power in a parallel processing environment
US7673164B1 · kind B1 · utility
64Cited by
2References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 13, 2005 |
| Grant date | Mar 2, 2010 |
| Priority date | — |
| Expiry date | Feb 12, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a plurality of tiles. Each tile includes a processor; a switch including switching circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles; and a timer. At least some tiles include a low power mode of operation in which either the processor or the switch is able to be powered down, and the tile is able to leave the low power mode based at least in part on a value of the timer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.