Interconnect delay fault test controller and test apparatus using the same

US7673203B2 · kind B2 · utility

Assignee

• Korea Electronics Technology Institute · KR

Inventors

• Chang Won Park · Suwon-si, KR
• Ki Man JEON · Seocho-gu, KR
• Young Hwan Kim · Seongnam-si, KR
• Jae Gi Son · Yongin-si, KR
• Hyun-Bean Yi · Seojong-myeon, KR
• Sung Ju Park · Seoul, KR

Key dates

• Filing date: Dec 27, 2006
• Grant date: Mar 2, 2010
• Expiry date: Apr 25, 2028

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/31855
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

An interconnect delay fault test controller and a test apparatus using the same wherein an update operation and a capture operation may be carried out in one interval of a system clock or a core clock when carrying out an interconnect delay fault test between an IEEE P1500 wrapped cores in a SoC as well as an interconnect wire on a board based on an IEEE 1149.1, and wherein the interconnect delay fault test using different system clocks or core clocks may be carried out simultaneously in one test cycle corresponding to each system clock or core clock even when multiple system clocks or core clocks exists is disclosed.