System and method for compile-time non-concurrency analysis
US7673295B1 · kind B1 · utility
28Cited by
12References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 27, 2004 |
| Grant date | Mar 2, 2010 |
| Priority date | — |
| Expiry date | Dec 27, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3604
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Compile-time non-concurrency analysis of parallel programs improves execution efficiency by detecting possible data race conditions within program barriers. Subroutines are modeled with control flow graphs and region trees having plural nodes related by edges that represent the hierarchical loop structure and construct relationship of statements. Phase partitioning of the control flow graph allows analysis of statement relationships with programming semantics, such as those of the OpenMP language, that define permitted operations and execution orders.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.