Multilevel semiconductor device and method of manufacturing the same
US7674660B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2006 |
| Grant date | Mar 9, 2010 |
| Priority date | — |
| Expiry date | Aug 11, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/481
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a multilevel semiconductor integrated circuit is provided, comprising: forming on a first active semiconductor structure a first plurality of transistors with respective gate structures disposed on a first substrate and source or drain regions disposed within the first substrate; depositing a first insulation layer on the first substrate and the gate structures; etching the insulation layer to form a plurality of openings exposing portions of the first substrate contacting the bottoms of the openings; forming a semiconductor seed layer filling the openings; forming an amorphous layer on the seed layer and the insulation layer; subjecting the first active semiconductor structure to at least one application of laser irradiation to transform the amorphous layer to a crystalline semiconductor layer having a protrusion region with a peak at or near the middle of two adjacent openings; forming on a second active semiconductor structure a second plurality of transistors with respective gate structures disposed on the crystalline semiconductor layer and forming a contact structure to electrically connect a transistor of the first active semiconductor structure to a …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.