Memory device and method of manufacturing the same
US7674661B2 · kind B2 · utility
3Cited by
4References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2007 |
| Grant date | Mar 9, 2010 |
| Priority date | — |
| Expiry date | Mar 27, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6211
Abstract
In a memory device and a method of manufacturing the memory device, a pair of channel layers included in the memory device may be formed on a sidewall of the sacrificial single crystalline layer pattern located on a protrusion of a semiconductor substrate. Accordingly, an etch damage may be reduced at the channel layer. The sacrificial single crystalline layer pattern may be removed to generate a void between the pair of the channel layers. As a result, a generation of a coupling effect may be reduced between the channel layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.