Thin film transistor array panel for liquid crystal display
US7675062B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2006 |
| Grant date | Mar 9, 2010 |
| Priority date | — |
| Expiry date | Sep 30, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/00
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A black matrix having an opening at pixels of a matrix array in a display area, a common wire including common pads and common signal lines, and gate pads in a peripheral area, and an alignment key in outer area to align interlayer thin films are formed on an insulating substrate. Red, blue and green color filters the edge of which overlap the black matrix are formed at the pixels on the insulating substrate, and an organic insulating layer covering the black matrix and the color filters and having a contact hole exposing the gate pad is formed thereon. A gate wire including a gate line connected to the gate pad through the contact hole and a gate electrode connected to the gate line is formed on the organic insulating layer, and a gate insulating layer covering the gate wire is formed on the organic insulating layer. A semiconductor pattern and ohmic contact layers are sequentially formed on the gate insulating layer of the gate electrode. A data wire including a source electrode and a drain electrode that are made of a same layer on the ohmic contact layers and separated from each other, and a data line connected to the source electrode and defining the pixels of a matrix array b…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.