Die warpage control
US7675182B2 · kind B2 · utility
6Cited by
2References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2007 |
| Grant date | Mar 9, 2010 |
| Priority date | — |
| Expiry date | Oct 8, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package comprises a substrate; a semiconductor die that comprises a set of one or more interconnects on one side to couple to the substrate; and a shape memory alloy layer provided on another side of the semiconductor die to compensate warpage of the semiconductor die. The shape memory alloy layer deforms with warpage of the semiconductor die and changes from the deformed shape to an original shape to flatten the semiconductor die in response to rise of a temperature during coupling of the die to the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.