Multi-phase delay locked loop with equally-spaced phases over a wide frequency range and method thereof
US7675333B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2007 |
| Grant date | Mar 9, 2010 |
| Priority date | — |
| Expiry date | Jun 10, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0812
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A Delay Locked Loop (DLL) and method for generating multiple equally spaced phases over a wide frequency range is disclosed. The DLL includes a delay line, and a control module. The delay line receives a reference clock signal and outputs a final delay clock signal in response to the reference clock signal. The delay line includes a plurality of delay cells connected in series. The plurality of delay cells generate a plurality of delay clock signals having equally spaced phases. The control module generates a phase control signal based on counting a number of pulses of the reference clock signal that are input to the delay line before occurrence of a first corresponding pulse of the final delay clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.