System and method for generating a delayed clock signal of an input clock signal
US7675339B2 · kind B2 · utility
2Cited by
6References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 9, 2007 |
| Grant date | Mar 9, 2010 |
| Priority date | — |
| Expiry date | Feb 21, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00026
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method for generating a delayed clock signal of an input clock signal involves selectively delaying the input clock signal to produce the delayed clock signal based on the duty cycle of the input clock signal and the duty cycle of a logic signal derived from a logic operation of the input clock signal and the delayed clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.