Video signal processing circuit, control method of video signal processing circuit, and integrated circuit
US7675522B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2004 |
| Grant date | Mar 9, 2010 |
| Priority date | — |
| Expiry date | Jan 11, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/395
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A display error occurs upon contention between writing of pixel data in a GRAM and reading of pixel data representing a scanning line including pixels which correspond to the pixel data above. Pixel data corresponding to pixels representing a scanning line stored in a latch circuit is displayed on a display panel, and when contention occurs between writing of pixel data in a GRAM and reading of pixel data corresponding to pixels representing a scanning line to the latch circuit from the GRAM, a controller delays reading of the pixel data corresponding to the pixels representing the scanning line and controls so as to perform reading of the pixel data corresponding to the pixels representing the scanning line to the latch circuit from the GRAM once again.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.