Semiconductor memory, test method of semiconductor memory and system
US7675773B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2008 |
| Grant date | Mar 9, 2010 |
| Priority date | — |
| Expiry date | Aug 28, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1802
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An address switch circuit receives a row address signal supplied to a first address terminal group and a column address signal supplied to a second address terminal group. Further, the address switch circuit receives the row address signal supplied to the second address terminal group and thereafter receives the column address signal supplied to the second address terminal group and supplies the received row address signal and the received column address signal to the row decoder and the column decoder during a second operation mode. The number of semiconductor memories that are tested at once can be increased by executing an operation test of the semiconductor memories in the second operation mode. In addition, it becomes possible to test a semiconductor memory using test assets for other semiconductor memories. Consequently, the test efficiency can be improved, and the test cost can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.