Patent · US Active

Chip circuit for combined and data compressed FIFO arbitration for a non-blocking switch

US7675930B2 · kind B2 · utility

0Cited by

5References

10Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Francois Abel · Thalwil, CH
Gottfried Goldrian · Eppelheim, DE
Ingemar Holm · Stuttgart, DE
Helmut Kohler · Mülheim, DE
Norbert Schumacher · Bad Liebenzell, DE

Key dates

Filing date	Feb 19, 2008
Grant date	Mar 9, 2010
Priority date	—
Expiry date	Aug 22, 2028

Classification

Technology area (CPC H)Electricity
CPC primaryH04L2012/5679
WIPO fieldDigital communication
WIPO sectorElectrical engineering

Abstract

A system for switching data packets through a multiple (m) input, multiple (n) output switching device providing switching having a fast one-cycle throughput. A respective switching device behaves like an output queued switch from a set of distributed output queues reading the incoming input control information from the plurality of input ports (IP) and compresses the information in a form which allows an easy association with a respective output port (OP) to which an individual input port is temporarily mapped.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.