Spread spectrum controllable delay clock buffer with zero cycle slip
US7676012B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2004 |
| Grant date | Mar 9, 2010 |
| Priority date | — |
| Expiry date | May 15, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03B23/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A controllable delay clock buffer that provides spread spectrum modulation of the output signals with zero cycle slip includes a PLL having a PLL loop filter that comprises an RC network. A clock signal is input to the PLL, and a SS modulation frequency is injected into the capacitor of the PLL loop filter. The SS signal is provided by a secondary charge pump that produces a programmable waveform such as a square wave or a stair case square wave current signal. The programmable waveform is integrated by the loop filter capacitor to form a corresponding triangular or trigonal waveform which varies the input to the VCO of the PLL to define a frequency modulation profile that has a corresponding triangular or trigonal envelope. The bandpass profile of the SS modulation signal is at a higher frequency range than the lowpass profile of the PLL, so that the SS waveform profile is not distorted or cancelled by the PLL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.